How to use conditional statements in VHDL: If-Then-Elsif-Else
Learn how to create branches in VHDL using the If, Then, Elsif, and Else statements. Depending on the result of an expression, the program can take different paths.
The syntax for the If statement is:
if [condition] then
[code inside of If-branch]
end if;
The condition may be a boolean or mathematical expression which evaluates to true or false. It may contain signals, variables, and constants. For example "counter = 5".
When using the simple If-statement, the code inside of the clause will be performed only if the condition evaluates to true. Otherwise, the program will continue directly to the next line after the "end if;".
The If-statement can be used in combination with the Elsif and Else statements.
The syntax for the If-Then-Elsif-Else statement is:
if [condition] then
[code]
elsif [alternative_condition] then
[code]
else
[code]
end if;
The Elsif statement may be used once or several times, or it may be omitted. The Else statement may be used once at the last branch, or it may be omitted. The Else branch will be chosen whenever any of the other Ifs or Elsifs conditions don't evaluate to true.
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