RTL: Digital design challenge to genrate pulse signal on each data toggle

System verilog / Verilog Interview QA Part 2

System verilog / Verilog Interview QA Part 1

I2C Protocol Part 8

Solution: Address Counter rollover condition

Interview Question: Address Counter rollover condition

Interview Questeion: Peak Detector Verilog Code

Solution: Optimization of Digital Design having comparator and subtractor

Do you really understand a Subtractor output ?????

Interview Question: Clock Divider FSM

Question Adder as a Subtractor

Digital Design Interview Question: Subtractor as Comparator

How to convert a 2:1 MUX into a OR gate?

Optimization of Digital Design having comparator, subtractor and MUX

Interview Question on Verilog Part 1

DigiThon Part 39

Digithon Solution Part 11

Digithon Solution Part 7

Digithon Solution Part 38

Digithon Part 38

Digithon Solution Part 2.1

Clock Gating | Integrated Clock Gating cell

Verilog Course Part 4

Verilog Course Part 3

Types of paths to be constrained